Researchers from the University of Tohoku, the University of Messina and the University of California, Santa Barbara (UCSB) have developed a scaled-up version of the stochastic spintron device probability computer (p-computer) suitable for complex computational tasks such as combinatorial. those. optimization and machine learning.
Moore’s Law predicts that computers will get faster every two years due to the evolution of semiconductor chips. While that’s what happened historically, the continuation of evolution is starting to lag behind. Revolutions in machine learning and artificial intelligence mean that much higher computing power is required. Quantum computing is one way to solve these problems, but significant obstacles remain to the practical application of scalable quantum computers.
A p-computer uses naturally occurring stochastic building blocks called probability bits (p-bits). Unlike bits in conventional computers, p-bits oscillate between states. The P-computer can operate at room temperature and acts as a domain-specific computer for a wide variety of applications in machine learning and artificial intelligence. Just as quantum computers try to solve inherently quantum problems in quantum chemistry, p-computers try to deal with the probabilistic algorithms commonly used for complex computational problems in combinatorial optimization and sampling.
Recently, researchers from Tohoku University, Purdue University and UCSB demonstrated that p-bits can be implemented efficiently using suitably modified spintronic devices called stochastic magnetic tunnel junctions (sMTJs). So far, sMTJ-based p bits have been implemented on a small scale; and only spintronic p-computer validated combinatorial optimization and machine learning concepts.
The research team presented two key developments at the 68th International Electronic Devices Meeting (IEDM), held on December 6, 2022.
First, they demonstrated how sMTJ-based p-bits could be combined with conventional and programmable semiconductor chips, namely field programmable gate arrays (FPGAs). The “sMTJ+FPGA” combination goes beyond the scope of previous small notations, making it possible to implement much larger p-bit networks in hardware.
Second, a probabilistic emulation of the quantum algorithm, simulated quantum annealing (SQA), was performed on “sMTJ+FPGA” heterogeneous p-computers with systematic evaluations for difficult combinatorial optimization problems.
The researchers also compared the performance of sMTJ-based p-computers with traditional computing hardware such as graphics processing units (GPUs) and tensor processing units (TPUs). They showed that p-computers using the high-performance sMTJ, previously demonstrated by a team at Tohoku University, can significantly increase efficiency and power consumption compared to conventional technologies.
“Currently, the s-MTJ+FPGA p-computer is a prototype with separate components,” said Professor Shunsuke Fukami, who was part of the research team. “Integrated p-computers using process-matched semiconductor magnetoresistive random access memory (MRAM) technologies may be possible in the future, but this will require a collaborative design approach with experts in materials, physics, circuitry and algorithms. Source
Source: Port Altele
